1. Field of the Invention
The present invention generally relates to the design of high performance very large scale integrated (VLSI) circuits such as microprocessors and, more particularly, to a computer-method for determining an optimal design for wiring interconnect and driver power. The method is run at the floor planning stage of the chip and may be run as the circuit design progresses.
2. Background Description
As cycle times in complementary metal oxide semiconductor (CMOS) processors becomes shorter, signal delays due to wire resistances are becoming a performance concern. Attempts have been made in some CMOS designs to solve this problem by utilizing large drivers and wires having wider widths than the minimum design values. While signal delays can be made shorter by increasing driver size and increasing wire widths, there are inherent dangers involved in this procedure. Driver size and line width are "expensive" commodities in chip design. One does not want to use either larger drivers or wider wires than absolutely necessary. For a given wire resistance and load combination, increasing driver size results in ever decreasing returns in delay while power consumption increases. The reason is that the wire resistance "shields" the load from the driver. There is a similar situation when wire width increases. The advantage in reducing delay by increasing wire width eventually diminishes as well because as wire resistance is reduced with increasing wire width, wire capacitance increases. There is therefore a need for a procedure to consistently choose driver sizes and wire widths so as to improve the delay in a manner which is affordable from a chip power and wiring budget point of view.